Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Expression

An expression calculates a value from a set of operators, names, literal values and sub-expressions. A static expression is an expression whose value can be calculated during compilation or elaboration.

Syntax

  {either}
  Expression Operator Expression
  Operator Expression
  (Expression)
  Name
  Number
  PhysicalLiteral
  Character
  String
  Aggregate
  QualifiedExpression
  New
  FunctionCall

Placement

 PACKAGE Pack IS
   ... 
 END PACKAGE Pack;
 PACKAGE BODY Pack IS
   ... 
 END PACKAGE BODY Pack;
 Blk:BLOCK 
   ... 
 BEGIN 
   ... 
 END BLOCK Blk;
 ENTITY Ent IS
   ... 
 BEGIN 
   ... 
 END ENTITY Ent;
 ARCHITECTURE Arc OF Ent IS
   ... 
 BEGIN 
   ... 
 END ARCHITECTURE Arc;
 CONFIGURATION Conf OF Ent IS
   ... 
 END CONFIGURATION Conf;
 Proc:PROCESS(...) 
   ... 
 BEGIN 
   ... 
 END PROCESS Proc;
 PROCEDURE P(...) IS
   ... 
 BEGIN 
   ... 
 END PROCEDURE P;
 FUNCTION F(...) RETURN Tp IS
   ... 
 BEGIN
   ... 
 END FUNCTION F;

Rules

Operators are evaluated in the following order: 1st: ** abs not 2nd: * / mod rem 3rd: + - & 4th: sll srl sla sra rol ror 5th: = /= < <= > >= 6th: and or xor nand nor xnor

Example

  A + B
  not A
  (A nand B) nor C
  A(7 downto 0)                          -- name
  '0'                                    -- character
  (others => '0')                        -- aggregate
  To_integer(V)                          -- function call
  T'(A, B)                               -- qualified expression
  new T
    

See Also

Operator, Name, Aggregate, New, Qualified Expression